1. Field of the Invention
This invention relates to a nonvolatile EPROM and more particularly to such an EPROM having a split gate (i.e., both a floating gate and a control gate) for controlling the writing and reading of each cell wherein the floating gate is self-aligned with the drain and the channel underlying the floating gate and the control gate is not self-aligned.
2. Prior Art
A split gate nonvolatile EPROM with increased efficiency is disclosed in U.S. Pat. No. 4,328,565 issued May 4, 1982 on an application of Harari, filed Apr. 7, 1980. As disclosed by Harari, the floating gate in an n channel EPROM cell extends over the drain diffusion and over a portion of the channel thereby to form a "drain" capacitance between the drain and the floating gate and a "channel" capacitance between the channel and the floating gate. A control gate then overlaps the floating gate and extends over the remainder of the channel near the source diffusion thereby to form a "control" capacitance between the floating gate and the control gate. These three capacitances form the coupling for driving each cell. The inversion region in the channel directly under the control gate is established directly by a "write or read access" voltage applied to the control gate. The inversion region in the channel directly under the floating gate is established indirectly through the drain and control capacitances and the channel capacitance by the control gate voltage and by another write access voltage applied to the drain. A cell is erased either by ultraviolet illumination or by electrons from the floating gate tunneling through a region of thinned oxide. The nonsymmetrical arrangement of the control gate and floating gate with respect to source and drain allows a very dense array implementation. Other split gate structures are disclosed in an article by Barnes, et al. entitled "Operation and Characterization of N-Channel EPROM Cells", published in Solid State Electronics, Vol. 21, pages 521-529 (1978) and an article by Guterman, et al. entitled "An Electrically Alterable Nonvolatile Memory Cell Using a Floating-Gate Structure", published in the IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 2, Apr. 1979.
FIG. 1 illustrates a typical EPROM of the prior art. In FIG. 1 a memory cell comprises n++ source region 11a and n++ drain region 11b separated by channel region 16. Channel region 16 has an effective length L.sub.eff as shown. Overlying channel region 16 is gate dielectric 12 on which is formed a floating gate 13. Typically floating gate 13 is formed of polycrystalline silicon. Overlying floating gate 13 is insulation 14, typically thermally grown silicon dioxide. Control gate 15 is formed above floating gate 13 on insulation 14. The state of the transistor in FIG. 1 is determined by the charge placed on floating gate 13. When electrons are placed on floating gate 13, the threshold voltage V.sub.tx required on gate 15 to turn on the transistor (i.e., to form an n channel between source 11a and drain 11b thereby allowing current to flow from one to the other) is much greater than when no electrons are placed on floating gate 13. As shown in FIG. 1, regions 13a and 13b of floating gate 13 overlie the source 11a and drain 11b, respectively, by a small amount ".DELTA.". Consequently, a capacitance is formed between the source 11a and floating gate region 13a and between the drain 11b and floating gate region 13b. If the overlap by gate 13 of the source 11a and the drain 11b is the amount ".DELTA.", then the capacitance C.sub.pp between the floating gate 13 and the control gate 15 (both made of polycrystalline silicon) is given by the following equation: EQU C.sub.pp .alpha.A.sub.pp .alpha.W(L.sub.eff +2.DELTA..sub.FG,D) (1)
In equation 1, C.sub.pp is the capacitance between the floating gate 13 and the overlying control gate 15 (this capacitance is proportional to A.sub.pp) and A.sub.pp, the area of the floating gate 13, is just the width W of the floating gate 13 (perpendicular to the sheet of the drawing) times the length of the floating gate 13 which is (L.sub.eff +2.DELTA..sub.FG,D).
The capacitance C.sub.PROM between the floating gate 13 and the substrate 10 is proportional to the effective width W.sub.eff (i.e. the width perpendicular to the sheet of the paper of the active area underneath the floating gate 13) of the floating gate 13 times L.sub.eff. Thus the capacitance C.sub.PROM is EQU C.sub.PROM .alpha.A.sub.PROM .alpha.W.sub.eff (L.sub.eff) (2)
The capacitive coupling C.sub.FG,D of the floating gate 13 to the drain 11b is given by EQU C.sub.FG,D .alpha.A.sub.FG,D .alpha.W.sub.eff (.DELTA..sub.FG,D) (3)
The coupling ratio CR.sub.FG,D of the capacitive coupling C.sub.FG,D of the floating gate 13 to drain 11b to the capacitive coupling C.sub.pp of the floating gate 13 to the control gate 15 and the capacitive coupling C.sub.PROM of the floating gate 13 to the substrate 10 is EQU CR.sub.FG,D .alpha.W.sub.eff (.DELTA..sub.FG,D)/[W.sub.eff (L.sub.eff)+W(L.sub.eff +2.DELTA..sub.FG,D)] (4)
As L.sub.eff becomes smaller and smaller the impact of the coupling of the drain on the performance of the PROM cell becomes greater and greater until in the limit, as L.sub.eff becomes very, very small, this coupling approaches 0.3 (taking into account different oxide thicknesses and the difference between W and W.sub.eff, for example). The overlay ".DELTA." depends on the process and is substantially fixed.
FIG. 2 shows the prior art split gate structure as illustrated by Harari in U.S. Pat. No. 4,328,565 issued May 4, 1982. The major concern in this structure relates to the length of portion 26b of channel 26 beneath floating gate 23. The structure of FIG. 2 is a nonself-aligned split gate structure. The total effective channel length 26 is defined by one mask and therefore is constant. Unfortunately, the length of the portion 26b of channel 26 beneath the floating gate 23 varies with mask alignment tolerances. Thus the effective channel length 26b depends strongly on the alignment process. As a result the best technology available today yields an effective tolerance of channel length 26b no better than .+-.0.5 to .+-.0.6 microns. For a typical nominal one micron effective channel length 26b the actual channel length will vary, due to manufacturing tolerances, over the range of about 1 .+-.0.6 micron. The result is a very wide variation in performance from one transistor memory cell to the next. Programming and read current are both very sensitive to channel length. Good cells will be perfect but bad cells will not work. A good device has an effective channel 26b (in one embodiment 0.8 microns) which lies between a too-short channel length (for example 0.2 microns or less, so that considering manufacturing variations there may not be any overlap at all of floating gate 23 over the channel 26 and thus there will be no programming of the cell) and a too-long channel length (for example greater than 1.4 microns) with unacceptably slow programming. The major issue in this prior art structure thus is the length of channel portion 26b (L.sub.eff) rather than the coupling. Therefore in a structure such as that shown in FIG. 2 there can be coupling between drain 21b and floating gate 23 but if the channel length 26b is not carefully controlled, the memory cell is not going to perform as expected.
A major problem in the prior art EPROM of FIG. 1 relates to the relationship between the program threshold voltage V.sub.tx and the drain turn on voltage V.sub.DTO of the device. V.sub.DTO is the voltage on the drain which, when capacitively coupled to the floating gate 13, turns on the transistor. As shown in FIG. 4, for L.sub.eff as shown in FIG. 1 increasing from about 0.5 to 1.2 microns, the program threshold V.sub.tx drops below the acceptable program threshold. On the other hand the drain turn-on voltage V.sub.DTO becomes as high as the junction breakdown voltage for L.sub.eff greater than about one micron. Below one micron, V.sub.DTO is very low and may go as low as three to five volts which causes the array of EPROMS to fail. The crossover point is shown as "A" in FIG. 4. In designing a regular EPROM, the crossover point A should be such that V.sub.tx is high enough (i.e. greater than five volts) while V.sub.DTO is not too low (i.e. not lower than eight volts). However, both curves V.sub.DTO and V.sub.tx are quite steep at the crossover point A and thus the characteristics of the device are very sensitive to L.sub.eff. So if the tolerance on L.sub.eff is even .+-.0.3 microns, which is very good, then the characteristics of the device are still relatively unpredictable. Obviously the desired solution is to eliminate the effect of V.sub.DTO and optimize L.sub.eff for V.sub.tx.